Abstract:

Square wave or quasi-square wave voltage may be suitable for low- and medium-power applications, but sinusoidal waveforms with minimum distortion are necessary for high-power applications. Harmonic content in the output of a dc–ac inverter can be reduced using either a filter circuit or pulse width modulation (PWM) techniques. Filters have the problem of being huge and expensive, whereas PWM approaches reduce or eliminate the need for filters, depending on the type of application. Traditional two-level pulse width modulation inverters produce less distorted current and voltage at the expense of larger switching losses due to high switching frequency. Traditional two-level high-frequency PWM inverters have a number of disadvantages, including the generation of common-mode voltages, higher switching losses, the need for switches with very short turn-on and turn-off times, a large dv/dt rating, the issue of voltage sharing in series connected devices, and the introduction of a large number of higher order harmonics. To overcome the mentioned issues, multilevel inverters have developed better equivalents to the traditional two-level pulse width modulated inverters. They also have a lower harmonic content at low switching frequencies, resulting in less switching stress on each device for high voltage, high power applications. On the basis of THDs and switching losses at various switching frequencies, this study explores two-level inverters, three-level & five-level diode clamped three-phase inverters. An comprehensive simulation study was conducted to optimize the switching frequency based on the corresponding switching losses and THD contents in line voltage have been presented in this thesis. A sinusoidal pulse width modulation (SPWM) technique is used for control.

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