Abstract:

A non-implantable Micro system typically is used to monitor activity of the brain. It requires on-chip real time processor which is processing of multi-channel neural signal with less power consumption and less area utilization. However, it is a challenge to get the less area and minimum consumption of power when the processing of multi-channel neural signal in real-time hardware with spike sorting algorithms. Hence, proposing an efficient neural signal processor (NSP) with optimal design constraints for multi-channel. The Haar discrete wavelet transform (HDWT) algorithm is designed for the NSP to process the spike data detection and sorting of the spikes. The NSP is simulated in Model Simulator 6.4a software and implemented on FPGA target device. The proposed NSP got 3.44ɳs of delay and 79.98mw% of power consumption when it is implemented on Cyclone FPGA device.  

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