Özet:

In this Paper, an efficient implementation of the direct form of the least mean square (LMS) adaptive filter algorithm is proposed. The conventional multiplier hinders the speed of the delayed LMS (DLMS) algorithm; hence latest high speed Vedic Multiplier is used for its high convergence rate, further, the Vedic Multiplier is explored for reducing the number of logic levels and timing levels, and possible reduction in logic delay. The efficient adders are used in digital signal processing applications to reduce the power requirement, area and delay. Vedic Multiplier and different adders (such as carry-increment, carry-look ahead, carry-select, ripplecarry and carry-skip adder) used to implement the DLMS algorithm are compared (a) with ripple-carry adder and vedic multiplier, (b) with vedic multiplier and carry-look ahead adder, (c) with Vedic multiplier and carryskip adder, (d) with Vedic multiplier and carry-increment adder, with (e) Vedic multiplier and carry-select adder based on their delay. Xilinx ISE is used for simulation and synthesis of the design with Spartan-6 FPGA, XC6SLX4-2TQG144.

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