Özet:

A complex programmable logic device (CPLD) based multilevel inverter has been designed and implemented. The design involves three main parts. The first part is the switching angle generator (SAG), which determines the switching angles from an optimized primitive angle. The second part is the switching pulse generator (SPG), which controls the drive circuit of the inverter. The timing circuit is the third part, which provides the necessary timing for both SAG and SPG. Implementing both SAG and SPG using a CPLD device mean high speed cycle time. Hence an accurate timing for the switching angles is obtained compared to other procedures that uses software for calculating and generating the switching angles, such as microcontroller. MATLAB work space has been used to acquire and analyze the inverter output via the PC sound card. Results of the implemented inverter staircase output voltage, as well as the output frequency spectrum are obtained.

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