Özet:

  Nowadays, Communication between chips is one of the fundamental problems in the Multi-Processor Systems (MPS). While many communication models concentrate on automation and efficiency, Photonic Network on Chip (PNoC) communication which is become a viable solution to a variety of problems facing modern computer in chip design; not only models focus on provide a high bandwidth, low latency medium for interconnection networks but also has the potential to deliver better power efficiency for the communications infrastructure. Many researchers have discussed PNoC in the literature. For different application areas, there are different technical issues that researchers are currently discussed such as: exploring and energy aware routing in hybrid optical network on chip, silicon photonic topologies (SPTs), and reconfigurable PNoC and follow on. Using the Multi-Layer Nano Photonic Interconnection Networks (MLNPIN) as if incorporate last promotion in silicon photonics and Three-Dimensional (3D) stacking technology. Other problem in photonic networks that the attention of many researchers has been attracted to lower power consumption in the optical interconnection network on chip are in routing problems these networks and engaged technology to overcome these problems covering its protocols, topology, floor plan and a low-power and low-cost optical router called optical turn around router. So, these networks with innovative approach increase performance and power with optoelectronic components for toward MPS. Ultimately, the current state of the art such topologies of photonic networks is captured in this paper, where solutions are discussed under their related to provide a high bandwidth and low latency medium for interconnection MPS. In this paper, we also point out the open research issues and intend to spark new interests and developments in the photonic interconnect topologies for MPS. 

Anahtar Kelimeler: