Özet:

Abstract Embedded real-time image processing applications are subject to strict design constraints concerning size and power. As devices scale down to nanoscale dimensions, circuit reliability becomes an increasingly pressing concern. Stochastic computing (SC) emerges as a cost-effective alternative to conventional deterministic binary computing, achieving this by encoding and processing information through digitized probabilities. This paper delves into the exploration of reconfigurable architectures to develop precise image-processing circuits for the compute-intensive blocks within baseline JPEG compression algorithms. These encompass RGB to YCbCr conversion, Discrete Cosine Transform (DCT), and Quantization, employing both deterministic and stochastic logic. Synthesis trial results underscore that stochastic implementation requires fewer hardware resources, occupies less physical area, and consumes less power when contrasted with deterministic logic. Employing an FPGA (PYNQ-Z2), the proposed designs have been executed, leading to power reductions of 112% and 120%, as well as area utilization improvements of 14% and 67.67%, for RGB to YCbCr and DCT-Quantization stochastic circuits, respectively, in comparison with deterministic circuits

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